Currently, people have developed various types of hardware accelerators to accelerate execution of some functions in a computer system. For example, a principle of a graphics accelerator is migrating all or some graphics functions from a processor to a dedicated hardware accelerator. Compared with the processor, the dedicated hardware accelerator can execute these graphics functions within shorter time. In addition, there are other types of hardware accelerators, such as an accelerator for processing an Extensible Markup Language, an accelerator for executing compression and decompression, a floating-point processor for executing a floating-point operation, and an accelerator for executing encryption and decryption. In general, any hardware that can execute a function allocated by a processor can be considered as a hardware accelerator.
In a wireless communications technology, to alleviate pressure of a baseband processor in a baseband chip, a baseband chip in an existing base station generally uses an algorithm accelerator to execute partial algorithm functions. With development of wireless communications technologies, an increasing number of baseband chips need to simultaneously support multiple communications standards, which include but are not limited to standards such as a Global System for Mobile Communications (Global System for Mobile Communications, GSM), a Universal Mobile Telecommunications System (Universal Mobile Telecommunications System, UMTS), time division duplex-Long Term Evolution (TDD-LTE), and frequency division duplex-Long Term Evolution (FDD-LTE). To simultaneously support algorithm processing of multiple communications standards, the algorithm accelerator in the existing baseband chip commonly uses a common-mode accelerator, for example, a common-mode accelerator simultaneously supporting the UMTS standard and the LTE standard, and a common-mode accelerator simultaneously supporting the GSM standard and the LTE standard. In addition, even if the algorithm accelerator supports only the LTE standard, the algorithm accelerator generally supports not only algorithm processing of the TDD-LTE standard and but also algorithm processing of the FDD-LTE standard. From a perspective of function implementation, an algorithm accelerator supporting the LTE standard is also a common-mode accelerator.
In the prior art, as shown in FIG. 1, a baseband chip including a common-mode accelerator is already developed, and may also be referred to as a multimode baseband system on chip (system on chip, SOC), where a single baseband chip supports only a single standard, for example, supports only the UMTS standard or supports only the LTE standard. However, such a baseband chip that includes a common-mode accelerator does not support chip-level multimode concurrence. For a multimode concurrence scenario, a solution of a combination of multiple baseband chips needs to be used to implement multimode concurrence at a board (also referred to as a printed circuit board) level. This solution not only wastes a processing capability of a multimode accelerator in each baseband chip, but also increases costs of base station boards due to use of multiple baseband chips.
Further, as shown in FIG. 2, the prior art provides another SOC chip supporting multimode concurrence, where single-mode/multimode algorithm accelerators are coupled to a baseband processor by using respective accelerator interfaces and buses. Processor cores of the baseband processor are separately responsible for different communications standards. Each communications standard is corresponding to a single-mode accelerator, for example, a GSM algorithm accelerator, a UMTS algorithm accelerator, or a TDD/FDD LTE algorithm accelerator. A common-mode accelerator, for example, a UL common-mode algorithm accelerator core, can be used by multiple processor cores at the same time. However, in different scenarios, to ensure that the common-mode accelerator maintains an expected processing capability for task requests of different communications standards, the processor cores need to communicate with each other to balance utilization of the processing capability of the common-mode accelerator among the different communications standards. In this case, if a processor core that is responsible for different communications standards accesses register space of a common-mode accelerator, it needs to be ensured that communications standards do not affect each other; otherwise, once an access error occurs, a register parameter of another communications standard is modified, that is, an error of one communications standard affects work of another communications standard. In addition, it also needs to be ensured that data, a message, an interrupt, and the like output when the common-mode accelerator processes a task of one communications standard do not occupy a resource of another communications standard, for example, data space, a sequence number of an interrupt; otherwise, an error of the another communications standard is caused. It can be seen that a process of communication between the processor cores is considerably complicated and prone to an error.